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1 copyright ? cirrus logic, inc. 2005 (all rights reserved) www.cirrus.com CS5351 108 db, 192 khz, multi-bit audio a/d converter features z advanced multi-bit de lta-sigma architecture z 24-bit conversion z 108 db dynamic range z -98 db thd+n z system sampling rate s up to 192 khz z 135 mw power consumption z high-pass filter and dc offset calibration z supports logic level s between 5 and 2.5 v z single-ended an alog inputs z overflow detection z pin compatible with the cs5361 general description the CS5351 is a complete analog-to-digital converter for digital audio systems. it performs sampling, analog-to- digital conversion, and anti-alias filtering. the device generates 24-bit values for both left and right inputs in serial form at sample rates up to 192 khz per channel. the CS5351 uses a 5th-order, multi-bit, delta-sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. the adc uses a differential architecture which provides excellent noise rejection. the CS5351 is ideal for audio systems requiring wide dy- namic range, negligible distortion, and low noise. these applications include a/v receivers, dvd-r, cd-r, digital mixing consoles, and effects processors. ordering in formation CS5351-ksz, lead free -10 to 70c 24-pin soic CS5351-kzz, lead free -10 to 70c 24-pin tssop CS5351-bzz, lead free -40 to 85c 24-pin tssop cdb5351 evaluation board voltage reference serial output interface digital filter high pass filter high pass filter decimation digital filter decimation dac - + s/h dac - + s/h ainr sclk sdout mclk rst vq3 lrck ainl filt+ i 2 s/lj m/s hpf mode0 mode1 refgnd v l mdiv lp filter lp filter ? ? ovfl vq1 vq2 feb ?05 ds565f1
CS5351 2 ds565f1 table of contents 1 characteristics and specifications ......................................................................... 4 specified operating conditions ................................................................................................ 4 absolute maximum ratings ................................. ..................................................................... 4 analog characteristics (CS5351-ksz/kzz)......... ..................................................................... 5 analog characteristics (CS5351-bzz).............. ........................................................................ 6 digital filter characteristics ................................................................................................. ..... 7 dc electrical characteristics .................................................................................................. .10 digital characteristics ................................... ..................................................................... ..... 10 thermal characteristics .................................... .................................................................... .. 10 switching characteristics - serial audio port.... ...................................................................... 11 2 pin descriptions ........................................................................................................... .... 14 3 typical connection diagram ....................................................................................... 15 4 applications ............................................................................................................... ........ 16 4.1 operational mode/sample ra te range select ................................................................ 16 4.2 system clocking ........................................................................................................... ... 16 4.2.1 slave mode ......................................................................................................... 16 4.2.2 master mode ....................................................................................................... 17 4.3 power-up sequence ........................................................................................................ 1 8 4.4 analog connections ........................................................................................................ .18 4.5 high pass filter and dc of fset calibration ..................................................................... 19 4.6 overflow detection ........................................................................................................ ... 19 4.6.1 ovfl output timing ........................................................................................... 19 4.7 grounding and power supply decoupling ....................................................................... 19 4.8 synchronization of multiple devices ................................................................................ 19 5 parameter definitions ................................................................................................... 20 6 package dimensions ..................................................................................................... 2 1 7 revision history ........................................................................................................... .... 23
CS5351 ds565f1 3 list of figures figure 1. single speed mode stopband rejection ......................................................................... 8 figure 2. single speed mode tr ansition band ............................................................................... 8 figure 3. single speed mode tr ansition band (detail).............. ..................................................... 8 figure 4. single speed mode passband ripple ............................................................................. 8 figure 5. double speed mode stopband rejectio n........................................................................ 8 figure 6. double speed mode transition band ...... ........................................................................ 8 figure 7. double speed mode transition band (d etail) ................................................................. 9 figure 8. double speed mode pa ssband ripple ............................................................................ 9 figure 9. quad speed mode stopband rejection . ......................................................................... 9 figure 10. quad speed mode transition band....... ........................................................................ 9 figure 11. quad speed mode transition band (d etail) .................................................................. 9 figure 12. quad speed mode passband ripple..... ........................................................................ 9 figure 13. master mode, left ju stified sai ................................................................................... 12 figure 14. slave mode, left justified sai ..................................................................................... 1 2 figure 15. master mode, i 2 s sai .................................................................................................. 12 figure 16. slave mode, i 2 s sai .................................................................................................... 12 figure 17. ovfl output timing .................................................................................................. .. 12 figure 18. left justified serial audio interface ............................................................................. 13 figure 19. i 2 s serial audio interface............................. ................................................................ 13 figure 20. ovfl output timing, i2s format ...... .......................................................................... 13 figure 21. ovfl output timing, left-justified format ................................................................. 13 figure 22. typical connection dia gram........................................................................................ 15 figure 23. CS5351 master mode clocking ................................................................................... 17 figure 24. CS5351 recommended an alog input buffer............................................................... 18 list of tables table 1. CS5351 mode control................................................................................................... .. 16 table 2. CS5351 slave mode clock ratios .................................................................................. 16 table 3. CS5351 common master clock frequencies................................................................. 17 table 4. revision history ..................................................................................................... ......... 23
CS5351 4 ds565f1 1 characteristics and specifications (all min/max characteristics and specif ications are guaranteed over the spec ified operating conditions. typical performance characteristics and specifications are derived from meas urements taken at typical supply voltages and t a = 25 c.) specified operat ing conditions (gnd = 0 v, all voltages with respect to 0 v.) absolute maximum ratings (gnd = 0 v, all voltages with respect to ground.) (note 1) notes: 1. operation beyond these limits may result in permanent damage to the device. normal operation is not gu aranteed at these extremes. 2. any pin except supplies. transient currents of up to 100 ma on the ana log input pins will not cause scr latch-up. 3. the maximum over/under voltage is limited by the input current. parameter symbol min typ max unit dc power supplies: positive analog positive digital positive logic va vd vl 4.75 3.1 2.37 5.0 3.3 3.3 5.25 5.25 5.25 v v v ambient operating temperature commercial (-ksz/-kzz) industrial (-bzz) t ac t ai -10 -40 - - 70 85 c c parameter symbol min max units dc power supplies: analog logic digital va vl vd -0.3 -0.3 -0.3 +6.0 +6.0 +6.0 v v v input current (note 2) i in -10 + 10 ma analog input voltage (note 3) v in gnd - 0.7 va + 0.7 v digital input voltage (note 3) v ind -0.7 vl + 0.7 v ambient operating temperature (power applied) t a -50 +95 c storage temperature t stg -65 +150 c
CS5351 ds565f1 5 analog characteristics (CS5351-ksz/kzz) (test conditions (unless otherwise specified): input test signal is a 1 khz sine wa ve; measurement bandwidth is 10 hz to 20 khz.) notes: 4. referred to the typi cal full-scale input voltage. parameter symbol min typ max unit single speed mode fs = 48 khz dynamic range a-weighted unweighted 102 99 108 105 - - db db total harmonic distortion + noise (note 4) -1 db -20 db -60 db thd+n - - - -98 -84 -44 -92 - - db db db double speed mode fs = 96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 102 99 - 108 105 102 - - - db db db total harmonic distortion + noise (note 4) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -98 -84 -44 -95 -92 - - - db db db db quad speed mode fs = 192 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 102 99 - 108 105 102 - - - db db db total harmonic distortion + noise (note 4) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -98 -84 -44 -95 -92 - - - db db db db dynamic performance for all modes interchannel isolation - 95 - db dc accuracy interchannel gain mismatch - 0.1 - db gain error -2 - 2 % gain drift -100 - 100 ppm/c offset error hpf enabled hpf disabled - - - - 0 100 lsb lsb analog input characteristics full-scale input voltage 0 .55*va 0.56*va .57*va vpp input impedance 7.5 - - k common mode reject ion ratio cmrr - 82 - db
CS5351 6 ds565f1 analog characteristi cs (CS5351-bzz) (test conditions (unless otherwise specified): input test signal is a 1 khz sine wave; m easurement bandwidth is 10 hz to 20 khz.) parameter symbo l min typ max unit single speed mode fs = 48 khz dynamic range a-weighted unweighted 100 97 108 105 - - db db total harmonic distortion + noise (note 4) -1 db -20 db -60 db thd+n - - - -98 -84 -44 -90 - - db db db double speed mode fs = 96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 100 97 - 108 105 102 - - - db db db total harmonic distortion + noise (note 4) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -98 -84 -44 -95 -90 - - - db db db db quad speed mode fs = 192 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 100 97 - 108 105 102 - - - db db db total harmonic distortion + noise (note 4) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -98 -84 -44 -95 -90 - - - db db db db dynamic performance for all modes interchannel isolation - 95 - db dc accuracy interchannel gain mismatch - 0.1 - db gain error -5 - 5 % gain drift -100 - 100 ppm/c offset error hpf enabled hpf disabled - - - - 0 100 lsb lsb analog input characteristics full-scale input voltage 0 .53*va 0.56*va 0.59*va vpp input impedance 7.5 - - k common mode reject ion ratio cmrr - 82 - db
CS5351 ds565f1 7 digital filter characteristics notes: 5. the filter frequency res ponse scales precisely with fs. 6. response shown is for fs equal to 48 kh z. filter characteristics scale with fs. parameter symbol min typ max unit single speed mode (2 khz to 51 khz sample rates) passband (-0.1 db) (note 5) 0 - 0.47 fs passband ripple -0.1 - 0.035 db stopband (note 5) 0.58 - - fs stopband attenuation -95 - - db total group delay (fs = output sample rate) t gd -12/fs- s interchannel phase deviation - 0.0001 - deg double speed mode (50 khz to 102 khz sample rates) passband (-0.1 db) (note 5) 0 - 0.45 fs passband ripple -0.1 - 0.035 db stopband (note 5) 0.68 - - fs stopband attenuation -92 - - db total group delay (fs = output sample rate) t gd -9/fs- s interchannel phase deviation - 0.0001 - deg quad speed mode (100 khz to 204 khz sample rates) passband (-0.1 db) (note 5) 0 - 0.24 fs passband ripple -0.1 - 0.035 db stopband (note 5) 0.78 - - fs stopband attenuation -92 - - db total group delay (fs = output sample rate) t gd -5/fs- s interchannel phase deviation - 0.0001 - deg high pass filter characteristics frequency response -3.0 db -0.13 db (note 6) -1 20 - - hz hz phase deviation @ 20 hz (note 6) - 10 - deg passband ripple - - 0 db filter settling time 10 5 /fs s
CS5351 8 ds565f1 figure 1. single speed mode stopband reject ion figure 2. single speed mode transition band -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00.10.20.30.40.50.60.70.80.91.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) figure 3. single speed mode transition band (detail ) figure 4. single speed mode passband ripple -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 5. double speed mode stopband rejection figure 6. double speed mode transition band -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 0.70 frequency (normalized to fs) amplitude (db)
CS5351 ds565f1 9 figure 7. double speed mode transition band (det ail) figure 8. double speed mode passband ripple -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.40 0.43 0.45 0.48 0.50 0.53 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 9. quad speed mode stopband rejectio n figure 10. quad speed mode transition band amplitude (db) frequency (normalized to fs) amplitude (db) frequency (normalized to fs) figure 11. quad speed mode transition band (det ail) figure 12. quad speed mode passband ripple amplitude (db) frequency (normalized to fs) frequency (normalized to fs) amplitude (db)
CS5351 10 ds565f1 dc electrical characteristics (gnd = 0 v, all voltages with respect to ground. mclk=12.288 mhz; master mode) notes: 7. power down mode is defined as rst = low with all clocks and data lines held static. 8. valid with the recommended capacitor values on filt+ and vq as shown in the typical connection diagram. digital characteristics thermal characteristics parameter symbol min typ max unit power supply current va = 5 v (normal operation) vl,vd = 5 v vl,vd = 3.3 v i a i d i d - - - 17.5 22 14.5 21.5 27.5 17 ma ma ma power supply current va = 5 v (power-down mode)(note 7) vl,vd = 5 v i a i d - - 100 100 - - a a power consumption (normal operation) va, vd, vl = 5 v va = 5 v, vl, vd = 3.3 v (power-down mode) - - - - - - 198 135 1 243 161 - mw mw mw power supply rejection ratio (1 khz) (note 8) psrr - 65 - db v q nominal voltage output impedance maximum allowable dc current source/sink - - - 2.5 25 0.01 - - - v k ma filt+ nominal voltage output impedance maximum allowable dc current source/sink - - - 5 15 0.01 - - - v k ma parameter symbol min typ max units high-level input voltage (% of vl) v ih 70% - - v low-level input voltage (% of vl) v il --30%v high-level output voltage at i o = 100 a(% of vl)v oh 70% - - v low-level output voltage at i o = 100 a(% of vl)v ol --15%v ovfl current sink i ovfl --4.0ma input leakage current (all pins except sclk and lrck) i in -10 - 10 a input leakage current (sclk and lrck) i in -25 - 25 a parameter symbol min typ max unit allowable junction temperature - - 135 c junction to ambient thermal impedance (multi-layer pcb) tssop (multi-layer pcb) soic (single-layer pcb) tssop (single-layer pcb) soic ja-tm ja-sm ja-ts ja-ss - - - - 70 60 105 80 - - - - c/w c/w c/w c/w
CS5351 ds565f1 11 switching characteristics - serial audio port (logic "0" = gnd = 0 v; logic "1" = vl, c l = 20 pf) parameter symbol min typ max unit output sample rate single speed mode double speed mode quad speed mode fs fs fs 2 50 100 - - - 51 102 204 khz khz khz ovfl to lrck edge setup time t setup 16/f sclk --s ovfl to lrck edge hold time t hold 1/f sclk --s ovfl time-out on overrange condition fs = 44.1, 88.2, 176.4 khz fs = 48, 96, 192 khz - - 740 680 - - ms ms mclk specifications mclk period t clkw 38 - 1953 ns mclk pulse duty cycle 40 50 60 % master mode sclk falling to lrck t mslr -20 - 20 ns sclk falling to sdout valid t sdo 0 - 32 ns sclk duty cycle - 50 - % slave mode single speed output sample rate fs 2 - 51 khz lrck duty cycle 40 50 60 % sclk period t sclkw 153 - - ns sclk duty cycle 45 50 55 % sclk falling to sdout valid t dss - - 32 ns sclk falling to lrck edge t slrd -20 - 20 ns double speed output sample rate fs 50 - 102 khz lrck duty cycle 40 50 60 % sclk period t sclkw 153 - - ns sclk duty cycle 45 50 55 % sclk falling to sdout valid t dss - - 32 ns sclk falling to lrck edge t slrd -20 - 20 ns quad speed output sample rate fs 100 - 204 khz lrck duty cycle 40 50 60 % sclk period t sclkw 77 - - ns sclk duty cycle 45 50 55 % sclk falling to sdout valid t dss - - 32 ns sclk falling to lrck edge t slrd -8 - 3 ns
CS5351 12 ds565f1 figure 13. master mode, left justified sai figure 14. sl ave mode, left justified sai sclk output t msl r sdout t sdo lrck output msb msb-1 clk input lrck input dss t msb msb-1 msb-2 t sclkw sdout srd l t figure 15. master mode, i 2 s sai figure 16. slave mode, i 2 s sai sclk input lrck input msb msb-1 t sclkw sdout srd l t dss t sclk input lrck input msb msb-1 t sclkw sdout srd l t dss t ovfl t setup lrck t hold figure 17. ovfl output timing
CS5351 ds565f1 13 figure 18. left justified serial audio interface sdata 23 22 7 6 23 22 sclk lrck 23 22 54 32 10 8 76 54 32 10 8 9 9 left channel right channel figure 19. i 2 s serial audio interface sdata 23 22 8 7 23 22 sclk lrck 23 22 65 43 21 0 87 65 43 21 0 9 9 left channel right channel figure 20. ovfl output timing, i 2 s format lrck ovfl sclk ovfl_r ovfl_l ovfl_r figure 21. ovfl output timing, left-justified format lrck ovfl sclk ovfl_r ovfl_l ovfl_r
CS5351 14 ds565f1 2 pin descriptions rst 124 filt+ m/s 223 refgnd lrck 322 vq3 sclk 421 ainr mclk 520 vq2 vd 619 va gnd 718 gnd vl 817 vq1 sdout 916 ainl mdiv 10 15 ovfl hpf 11 14 m1 i 2 s/lj 12 13 m0 pin name # pin description rst 1 reset ( input ) - the device enters a low power mode when low. m/s 2 master/slave mode (input) - selects operation as either clock master or slave. lrck 3 left right clock ( input / output ) - determines which channel, left or right, is currently active on the serial audio data line. sclk 4 serial clock ( input / output ) - serial clock for the serial audio interface. mclk 5 master clock ( input ) - clock source for the delta-sig ma modulator and digital filters. vd 6 digital power ( input ) - positive power supply for the digital section. gnd 7,18 ground ( input ) - ground reference. must be connected to analog ground. vl 8 logic power ( input ) - positive power for the digital input/output. sdout 9 serial audio data output ( output ) - output for two?s complement serial audio data. mdiv 10 mclk divider (input ) - enables a master clock divide by two function. hpf 11 high pass filter enable (input ) - enables the digital high-pass filter. i 2 s/lj 12 serial audio interface format select ( input ) -selects either the left-justified or i 2 s format for the sai. m0 m1 13, 14 mode selection ( input ) - determines the operational mode of the device. ovfl 15 overflow (output, open drain) - detects an overflow condition on both left and right channels. ainl ainr 16, 21 analog inputs ( input ) - the full-scale analog input level is spec ified in the analog characteristics speci- fication table. vq1 vq2 vq3 17, 20, 22 quiescent voltage (output) - filter connection for the internal quiescent reference voltage. va 19 analog power ( input ) - positive power supply for the analog section. ref_gnd 23 reference ground ( input ) - ground reference for the internal sampling circuits. filt+ 24 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits.
CS5351 ds565f1 15 3 typical connection diagram filt+ ainl v d 0.01 f a/d converter sclk CS5351 m/s mclk ainr 47 f + rst va v l +5v 1 f +5v to 2.5v 5.1 1 f + + + sdout gnd i 2 s/lj lrck gnd power down and mode settings audio data processor timing logic and clock 0.01 f hpf m0 m1 refgnd mdiv +5 v to 3.3 v 1 f analog input buffer (figure 24) ovfl vl 10 k * resistor may only be used if vd is derived from va. if used, do not drive any other logic from vd * 0.01 f 0.01 f 0.01 f vq1 vq3 vq2 figure 22. typical connection diagram
CS5351 16 ds565f1 4 applications 4.1 operational mode/sampl e rate range select the output sample rate, fs, can be adjusted from 2 khz to 204 khz. the CS5351 must be set to the proper speed mode via the mode pins, m1 and m0. refer to table 1. 4.2 system clocking the device supports operation in either master mode, wher e the left/right and serial clocks are synchronously gen- erated on-chip, or slave mode, which requires external gener ation of the left/right and serial clocks. the device also includes a master clock divider in ma ster mode where the master clock will be internally divid ed prior to any other internal circuitry when mdiv is enabled, set to logic 1. in slave mode, the mdiv pin needs to be disabled, set to logic 0. 4.2.1 slave mode lrck and sclk operate as inputs in slave mode. the lef t/right clock must be synchronously derived from the mas- ter clock and be equal to fs. it is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x fs to maximize system performance. refer to table 2 for required clock ratios. table 2. CS5351 slave mode clock ratios m1 (pin 14) m0 (pin 13) mode output sample rate (fs) 0 0 single speed mode 2 khz - 51 khz 0 1 double speed mode 50 khz - 102 khz 1 0 quad speed mode 100 khz - 204 khz 11reserved table 1. CS5351 mode control single speed mode fs = 2 khz to 51 khz double speed mode fs = 50 khz to 102 khz quad speed mode fs = 100 khz to 204 khz mclk/lrck ratio 256x, 512x 128x, 256x 128x sclk/lrck ratio 32x, 64x, 128x 32x, 64x 32x, 64x
CS5351 ds565f1 17 4.2.2 master mode in master mode, lrck and sclk operate as outputs. the lef t/right and serial clocks are internally derived from the master clock with the left/right clock equal to fs and the se rial clock equal to 64x fs, as shown in figure 23. refer to table 3 for common master clock frequencies. 128 256 64 m0 m1 lrck output (equal to fs) single speed quad speed double speed 00 01 10 2 4 1 sclk output single speed quad speed double speed 00 01 10 2 1 0 1 mclk mdiv figure 23. CS5351 master mode clocking sample rate (khz) mdiv = 0 mclk (mhz) mdiv = 1 mclk (mhz) 32 8.192 16.384 44.1 11.2896 22.5792 48 12.288 24.576 64 8.192 16.384 88.2 11.2896 22.5792 96 12.288 24.576 176.4 11.2896 22.5792 192 12.288 24.576 table 3. CS5351 common master clock frequencies
CS5351 18 ds565f1 4.3 power-up sequence reliable power-up can be accomplished by keeping the devic e in reset until the power supplies, clocks and config- uration pins are stable. it is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. the internal reference voltage must be stable for the devi ce to produce valid data. t herefore, there is a delay be- tween the release of reset and the generation of valid out put, due to the finite output impedance of filt+ and the presence of the external capacitance. 4.4 analog connections the analog modulator sa mples the input at 6.144 mhz. the digital filter will reject signals within the stopband of the filter. however, there is no reje ction for input signals which are (n 6.144 mhz) the digital passband frequency, where n=0,1,2,...refer to figure 24 which shows the suggested filter th at will attenuate any noise energy at 6.144 mhz, in addition to providing the optimum source impedance for the modulators. the use of capacitors which have a large voltage coefficient (such as general purpos e ceramics) must be avoided since these can degrade signal linearity. figure 24. CS5351 recommended analog input buffer ainl vq1 vq3 - + 470 pf c0g CS5351 634 91 2700 pf c0g 1 f 1 f 100 k 100 k 1 f 0.01 f ainr 2700 pf c0g - + 470 pf c0g 91 634 - + vq2 100 k 100 k
CS5351 ds565f1 19 4.5 high-pass filter and dc offset calibration the operational amplifiers in the input circuitry driving the CS5351 may generate a small dc offset into the a/d con- verter. the CS5351 includes a high pass filter after the decimator to remove any dc offset which could result in recording a dc level, possibly yielding "clicks" when switching between devices in a multichannel system. the high pass filter continuou sly subtracts a measure of the dc offset from the output of the decimation filter. if the hpf pin is taken high during normal operation, the current valu e of the dc offset register is frozen and this dc offset will continue to be subtracted from th e conversion result. this feature ma kes it possible to perform a system dc offset calibration by: running the CS5351 with the high pass filter enabled until the filter settles. see the digital filter characteristics for filter settling time. disabling the high pass filter and freezing the stored dc offset. a system calibration performed in this way will eliminate offsets anywhere in th e signal path between the calibration point and the CS5351. 4.6 overflow detection the CS5351 includes overflow detection on both the left and right channels. this time multiplexed information is presented as open drain, active low on pin 15, ovfl . the ovfl_l and ovfl_r data will go to a logical low as soon as an overrange condition in either channel is detected. the data will remain low as spec ified in the switching char- acteristics - serial audio port section. this ensures sufficie nt time to detect an overrange condition regardless of the speed mode. after th e timeout, the ovfl_l and ovfl_r data will return to a logical hi gh if there has not been any other overrange condition detected. pleas e note that an overrang e condition on either ch annel will restart the time- out period for both channels. 4.6.1 ovfl output timing in left-justified format, the ovfl pin is updated one sclk period after an lrck transition. in i 2 s format, the ovfl pin is updated two sclk periods after an lrck transition. refer to figures 23 and 24. in both cases the ovfl data can be easily demultiplexed by using th e lrck to latch the data. in left-just ified format, the rising edge of lrck would latch the right channel overflow status, and the fa lling edge of lrck would latch the left channel overflow status. in i 2 s format, the falling edge of lrck would latch the ri ght channel overflow stat us and the ri sing edge of lrck would latch the left channel overflow status. 4.7 grounding and powe r supply decoupling as with any high resolution converter, the CS5351 requires careful attention to power supply and grounding arrange- ments if its potential performance is to be realized. figure 22 shows the recommended power arrangements, with va and vl connected to clean supplies. vd, which powers the digital filter, ma y be run from the system logic supply or may be powered from the analog supply via a resistor. in this case, no additional devices should be powered from vd. decoupling capacitors should be as near to the ad c as possible, with the low va lue ceramic capacitor being the nearest. all signals, especially clocks, should be kept away from the filt+ and vq pins in order to avoid un- wanted coupling into the modulators. the filt+ and vq decoupling capacitors, particularly the 0.01 f, must be positioned to minimize the electric al path from filt+ and refgnd. the cdb5351 evaluation board demonstrates the optimum layout and power supply arrangements. to mini mize digital noise, connect the adc digital outputs only to cmos inputs. 4.8 synchronization of multiple devices in systems where multiple a dcs are required, care must be taken to achieve simultaneous sampling. to ensure synchronous sampling, the mclk and lrck must be the sa me for all of the CS5351?s in the system. if only one master clock source is needed, one solution is to plac e one CS5351 in master mode, and slave all of the other CS5351?s to the one master. if multiple master clock source s are needed, a possible solution would be to supply all clocks from the same external source and time the CS5351 reset with the inactive edge of mclk. this will ensure that all converters begin sampling on the same clock edge.
CS5351 20 ds565f1 5 parameter definitions dynamic range the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise rati o measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is added to resulting me asurement to refer the measurement to full-scale. this technique ensures that the di stortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic indu stries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including dist ortion components. expressed in decibels. measured at -1 and -20 dbfs as sug gested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right cha nnels. measured for each channel at the converter's output with no signal to the input under test and a fu ll-scale signal applied to th e other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale ana log output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111... 111 to 000...000) from the ideal. units in mv.
CS5351 ds565f1 21 6 package dimensions inches millimeters dim min max min max a 0.093 0.104 2.35 2.65 a1 0.004 0.012 0.10 0.30 b 0.013 0.020 0.33 0.51 c 0.009 0.013 0.23 0.32 d 0.598 0.614 15.20 15.60 e 0.291 0.299 7.40 7.60 e 0.040 0.060 1.02 1.52 h 0.394 0.419 10.00 10.65 l 0.016 0.050 0.40 1.27 0 8 0 8 24l soic (300 mil bo dy) package drawing d h e b a1 a c l seating plane 1 e
CS5351 22 ds565f1 notes: 1.?d? and ?e1? are reference datums and do not in cluded mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2.dimension ?b? does not include dambar protrusion/ intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximu m material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3.these dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters not e dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.303 0.307 0.311 7.70 7.80 7.90 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 24l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
CS5351 ds565f1 23 7 revision history contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the informatio n is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are ad vised to obtain the lates t version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject t o the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnif ication, and limitation o f liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the bas is for manufacture or sale o f any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furn ishing this information, cirru s grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intel lectual property rights . cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the info rmation only for us e within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such a s copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may invo lve potential risks of death, personal injury, or severe property or environmental damage (?critical applic ations?). cirrus products ar e not designed, authorized or warranted for use in aircraft systems, military applica tions, products surgically implanted into the body, a utomotive safety or security devices, life support products or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any a nd all liability, including attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. release date changes pp2 sept 2002 preliminary datasheet. f1 feb 2004 improve gain error specification under analog characteristics. specify full-scale input voltage in terms of va under analog characteristics. update differential input impedanc e under analog characteristics. increase maximum power-supply current, i a , under dc electrical characteristics. reduce maximum power consumption unde r dc electrical characteristics. update filt+ output impedance specificatio n under dc electric al characteristics. extend maximum fs in single-speed mode to 51 khz. extend maximum fs in double-speed mode to 102 khz. extend maximum fs in quad-speed mode to 204 khz. decrease maximum sclk falling to lrck edge specification in quad-sp eed mode. replace minimum mclk high/low timing spec ifications with duty cycle specification. replace minimum sclk high/low timing specifications with duty cycle specification. replace recommended analog input buffer with new input buffer topology. table 4. revision history

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